Josep Torrellas

Torrellas leads the i-acoma architecture group.
The main emphasis is on designing The Bulk Multicore Architecture.
See our White Paper on the Bulk Multicore Architecture.
See what the EE Times says about the Bulk Multicore.

Some Recent Publications:

• BlueShift: Designing Processors for Timing Speculation from the Ground Up, HPCA, March 2009.
• Capo: Abstractions and Software-Hardware Interface for Hardware-Assisted Deterministic Multiprocessor Replay, ASPLOS, March 2009.
• SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization, IEEE Micro Top Picks, January-February 2009.
• Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently, CACM, 2009.
• Techniques to Mitigate the Effects of Congenital Faults in Processors, 160 pages, ISBN: 978-3-639-04637-3, VDM Verlag, 2008.
• Facelift: Hiding and Slowing Down Aging in Multicores, MICRO, November 2008.
• EVAL: Utilizing Processors with Variation-Induced Timing Errors, MICRO, November 2008.

Software Released:

• VARIUS: A model of within-die process variation and resulting timing errors in processors for microarchitects.
• SESC: A cycle accurate architectural simulator that models a very wide set of architectures: superscalars, multiprocessors, processors in memory, and thread-level speculation.

Research Interests:

Professor Torrellas leads The i-acoma Group, which focuses on new processor, memory, and system technologies and organizations to build novel multiprocessor computer architectures. The goal is to design high-performance multiprocessor computers that are very easy to program, inexpensive, and built out of commodity components.

The main emphasis is on several areas:

• Multiprocessor organization and system design
• Speculative multithreading
• Hardware reliability and variability
• Support for software reliability
• Low-power design
• Old Projects
• The FlexRAM Intelligent Memory System
• The Morphable Multithreaded Memory Tiles (M3T) architecture

Professor Torrellas is also involved in the related project The Polaris parallelizing compiler.

Currently Teaching:

CS533: Parallel Computer Architectures.

Contact Information

Josep Torrellas
4231 Thomas M. Siebel Center for Computer Science.
University of Illinois.
201 N. Goodwin.
Urbana, IL. 61801-2302.
Phone (217) 244-4148, fax 217-265-6582.
E-mail: torrellas@cs.uiuc.edu.

Administrative Assistant

Sheila Clark,
Thomas M. Siebel Center for Computer Science.
University of Illinois.
201 N. Goodwin.
Urbana, IL. 61801-2302.
Phone (217) 244-6621, fax 217-265-6582.
E-mail: sdclark@cs.uiuc.edu.