CS232: Computer Architecture II
Fall 2008
Tentative Schedule


This is subject to modifications, and is only intended to give you an idea of how wonderful the semester will be.

Last update: 8/25/08

Week

Date

Lecture/Section Topic

Reading (2nd ed.)

Reading (3rd ed.)

  1

8/25 SECT

CS232 & Bit-wise Logical Programming

 

 

8/27

MIPS Introduction

3.1-3.3, 3.7

2.1-2.3, 2.8

8/29

MIPS loops

3.5

2.6

  2

9/3

More MIPS instructions

3.8

2.9

9/5

Procedures in MIPS

3.6, A.5-A.6

2.7, A.5-A.6

  3

9/8 SECT

Recursion

3.10

2.13

9/10

Machine Language & Pointers

3.4, 3.11

2.4, 2.15

9/12

I/O, Exceptions and Interrupts

5.6, 6.7, 8.5

5.6, 6.8, 8.5

  4

9/15 SECT

Writing Interrupt Handlers

 

 

9/17

Compilers, Assemblers and Linkers

1.1-1.2, 3.9, A.2-A.4

1.1-1.2, 2.10, A.2-A.4

9/19

Floating Point

4.8-4.9

3.6-3.7

  5

9/22 SECT

Little vs. Big Endian

3.3, Appendix A p.48

2.3, Appendix A p.43

9/24

Computer Arithmetic review and Single-cycle Datapath intro

4.1-4.5, 4.10-4.12

3.1-3.3, 2.5, B.4-B.5, 3.8-3.10

9/26

Single-cycle Datapath and its Performance

1.3-1.6, 5.1-5.3

1.3-1.5, 5.1-5.4

  6

9/29 SECT

Single-cycle Datapath extensions

 

 

10/1

Exam 1

 

 

10/3

Pipelining introduction

6.1 (to p. 440)

6.1 (to p. 374)

  7

10/6 SECT

Processor Performance

 

 

10/8

Pipelined CPU implementation

6.2-6.3

6.2-6.3

10/10

Data hazards and forwarding

6.1, 6.4

6.1, 6.4

  8

10/13 SECT

Pipelining examples

 

 

10/15

Control hazards and stalling

6.1, 6.5-6.6

6.1, 6.5-6.6

10/17

Control Hazards and stalling Cont.

 

 

  9

10/20 SECT

Hazard examples

 

 

10/22

Cache introduction

7.1-7.2

7.1-7.2

10/24

More Cache Organizations

 

 

  10

10/27 SECT

Cache performance and multi-level caches

 

 

10/29

Exam 2

7.2-7.3

7.2-7.3

10/31

Working sets and Cache Performance

7.5

7.5

  11

11/3 SECT

Block sizes, associativity

 

 

11/5

Virtual Memory

7.4

7.4

11/7

Introduction to I/O and Hard Disks

8.1-8.3

8.1, 8.6, 8.2 through pg. 571, 8.3

  12

11/10 SECT

Parity and ECC

Appendix B: pp34-35

Appendix B: pp65-66

11/12

Programming for Performance

 

 

11/14

RISC vs. CISC and the x86 assembly language

3.12, 3.15

2.16, 2.19

  13

11/17 SECT

Performance Tuning with Vtune

 

 

11/19

Exam 3

 

 

11/21

Explicit Parallelism and SIMD operations

 

 

    14

                                                                                                Thanksgiving Break

  15

12/1 SECT

Using x86 and MMX

 

 

12/3

Multi-core Architectures, TLP, and OpenMP

 

 

12/5

Hardware Primitives for Atomic Operations

 

 

  16

SECT

 

12/10

Modern CPU implementations (optional lecture)

6.9-6.12

6.10-6.13

  17

Final Exam

Tentatively scheduled for Tuesday 12/16 13:30-16:30

 

 


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