This is subject to modifications, and is only intended to give you an idea
of how wonderful the semester will be.
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Date
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Lecture/Section
Topic
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Reading (2nd ed.)
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Reading (3rd ed.)
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1
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8/25 SECT
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CS232 & Bit-wise Logical Programming
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8/27
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MIPS Introduction
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3.1-3.3, 3.7
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2.1-2.3, 2.8
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8/29
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MIPS loops
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3.5
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2.6
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2
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9/3
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More MIPS instructions
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3.8
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2.9
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9/5
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Procedures in MIPS
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3.6, A.5-A.6
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2.7, A.5-A.6
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3
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9/8 SECT
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Recursion
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3.10
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2.13
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9/10
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Machine Language & Pointers
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3.4, 3.11
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2.4, 2.15
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9/12
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I/O, Exceptions and Interrupts
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5.6, 6.7, 8.5
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5.6, 6.8, 8.5
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4
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9/15 SECT
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Writing Interrupt Handlers
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9/17
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Compilers, Assemblers and Linkers
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1.1-1.2, 3.9, A.2-A.4
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1.1-1.2, 2.10, A.2-A.4
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9/19
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Floating Point
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4.8-4.9
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3.6-3.7
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5
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9/22 SECT
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Little vs. Big Endian
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3.3, Appendix A p.48
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2.3, Appendix A p.43
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9/24
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Computer Arithmetic review and Single-cycle Datapath
intro
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4.1-4.5, 4.10-4.12
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3.1-3.3, 2.5, B.4-B.5, 3.8-3.10
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9/26
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Single-cycle Datapath and its Performance
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1.3-1.6, 5.1-5.3
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1.3-1.5, 5.1-5.4
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6
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9/29 SECT
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Single-cycle Datapath extensions
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10/1
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Exam 1
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10/3
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Pipelining introduction
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6.1 (to p. 440)
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6.1 (to p. 374)
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7
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10/6 SECT
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Processor Performance
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10/8
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Pipelined CPU implementation
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6.2-6.3
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6.2-6.3
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10/10
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Data hazards and forwarding
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6.1, 6.4
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6.1, 6.4
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8
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10/13 SECT
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Pipelining examples
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10/15
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Control hazards and stalling
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6.1, 6.5-6.6
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6.1, 6.5-6.6
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10/17
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Control Hazards and stalling Cont.
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9
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10/20 SECT
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Hazard examples
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10/22
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Cache introduction
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7.1-7.2
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7.1-7.2
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10/24
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More Cache Organizations
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10
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10/27 SECT
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Cache performance and multi-level caches
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10/29
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Exam 2
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7.2-7.3
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7.2-7.3
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10/31
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Working sets and Cache Performance
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7.5
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7.5
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11
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11/3 SECT
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Block sizes, associativity
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11/5
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Virtual Memory
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7.4
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7.4
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11/7
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Introduction to I/O and Hard Disks
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8.1-8.3
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8.1, 8.6, 8.2 through pg. 571, 8.3
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12
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11/10 SECT
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Parity and ECC
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Appendix B: pp34-35
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Appendix B: pp65-66
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11/12
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Programming for Performance
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11/14
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RISC vs. CISC and the x86 assembly language
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3.12, 3.15
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2.16, 2.19
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13
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11/17 SECT
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Performance Tuning with Vtune
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11/19
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Exam 3
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11/21
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Explicit Parallelism and SIMD operations
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14
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Thanksgiving Break
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15
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12/1 SECT
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Using x86 and MMX
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12/3
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Multi-core Architectures, TLP, and OpenMP
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12/5
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Hardware Primitives for Atomic Operations
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16
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SECT
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12/10
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Modern CPU implementations (optional lecture)
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6.9-6.12
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6.10-6.13
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17
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Final Exam
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Tentatively scheduled for
Tuesday 12/16 13:30-16:30
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